Digital Logic Design

Octera has a wealth of experience in Logic Design and Synthesis ranging from FPGAs to hierarchical ASIC and SOC environments incorporating multiple clock domains.

We understand the issues presented by deep submicron process geometries and can leverage our knowledge to minimize your learning curve and risk. We are capable of analyzing and recommending improvements to your current processes through taking full responsibility for your Integrated Circuit designs.

• Logic Design
  • Micro-architecture
  • Efficient Coding
  • Verilog, VHDL, Proprietary HDLs
  • Schematic capture
  • FPGA to ASIC conversions
• Synopsys Design Compiler
  • Hierarchical ASIC and SOC synthesis
  • Hierarchical synthesis methodologies
  • dc_shell script automation
  • tcl_shell script automation
  • Post-route ECOs
• Synopsys Design Time/Prime Time
  • Static timing analysis
• Synopsys Test Compiler/TetraMAX/BSD Compiler/DFT Compiler
  • ATPG vector generation
  • IEEE 1149.1 boundary scan insertion, verification, and vector generation
  • Scan insertion
• Synopsys Library Compiler
  • Synopsys libraries created for your custom cells
  • Custom wire models and operating conditions
  • Synopsys library compilation
• Synplicity Synplify
• Viewlogic FPGA Express

About Us

• ASIC design
• FPGA design
• General design
• Board design
• Design re-use
• Design tools
• Digital logic
• System definition
• System-on-a-chip
• Verification