When to Use an Independent Design Group
The first decision is whether an independent group is needed or not. If you have all the skills and manpower you need internally the answer is obviously not to. But remember, even using a new tool flow on a well understood technology will involve a learning curve.
We typically expect a good back-end ASIC engineer to take one year to really master a new tool set - admittedly the most complex environment one can encounter. Aside from these gray areas, use of an independent group is usually pretty easy to decide - to boost manpower, add skills or deal with short term workloads. Once that decision has been made, the next question is at what point to bring in the independent group?
Simply put - as early in the design process as possible. Of course that's an easy statement to make and the reality will vary a great deal depending on the project and the circumstances. However, remember you are using a third party for a reason - to add skills, knowledge and manpower to your own team. Very often they will be able to bring experience in other projects they have seen to bear on your design. Sometimes this can help avoid decisions being made that prove costly later in the process. For example; a common design technique is to prototype ASIC designs in FPGAs.
We have seen examples of IP being used in the FPGA prototype that cannot be licensed to an ASIC technology. Whilst by no means wrong, such a decision will require significant design changes in the move to ASIC, adding cost and time to the project. Other ways can be found to solve these sorts of problems and it is in these areas that independent groups often add value. Looking at different design jobs, third parties can be used in different ways:
FPGA design
FPGAs have made huge strides in density and complexity in recent years. As a result, projects that before could have easily been completed by a single engineer have become multi-person efforts similar to ASIC designs in complexity. FPGAs also have the seducing feature that they can be re-programmed at anytime. This has led many a designer to debug their design on the bench rather than spend more time in simulation - a practice we would strongly advise against for designs of any complexity.
An ideal FPGA project follows almost ASIC type flow of definition - specification - coding - verification with the final stage of translating the design into an actual chip being carried out almost instantaneously. Undoubtedly FPGAs will grab a continuing share of the market, but the skills to use them will become more complex and specialized.
Use independent design services for FPGA development in the following areas:
- To obtain experienced FPGA design personnel - it takes time to learn the tools effectively
- To use FPGA features you may be unfamiliar with; embedded processors and on-chip SERDES for example
- To help with the verification - on a large FPGA probably more than 50% of the actual work
- To access experience in particular design areas; 10G Ethernet, DSP functions, real-time operating systems are all examples of complex designs that can be implemented on a modern FPGA - but experience in doing so will save a great deal of time.
Structured ASIC and ASIC
Structured ASIC and ASIC technologies need some third party design services for every design - somebody has to take the design and turn it into an actual chip that can be manufactured.
Very, very few companies have or want the ability to take a design all the way to a GDS2 file in the modern world. Doing so requires some highly expensive and complex tools as well as a very specific class of engineering staff.
However there are additional areas where a third party design team can be very beneficial:
- In initial sizing of the design. Third parties often have all the ASIC tools installed which can save an enormous amount of time getting a code size estimate if the particular tools flow is not immediately available internally.
- Selecting Intellectual Property. Often a critical part of the design and in an ASIC, not an area where mistakes can be made.
- In coding and verification. A formal test plan should be part of any ASIC development and verification should take about 70% of the front-end design time.
- Clock and scan insertion and ATPG generation. These tasks are sometimes carried out by customer engineering groups, but again they require some specialized tools and knowledge.
Finally we should mention the increasing trend to handing over complete chip development to an independent team. The reality is that the number of ASIC design starts per year continues to decline as FPGAs grow and grow in complexity. Maintaining a skilled ASIC design team in-house just may not be an options for one or two designs per year.
Full system design
Creating a full system using third party engineering generally requires one or more of the disciplines already discussed, combined with general hardware engineering such as PCB design. Out-sourcing these tasks usually makes most sense when the interaction between the different components is complex and design of one (say the ASIC) will heavily influence some of the others (say the PCB layout). A common example of this is the modern trend toward using SERDES technology to interconnect signals chip-to-chip. With data rates at 4Gbit / sec and more, the PCB layout of such a system becomes a critical factor.
If looking to use a third party design house to do a complete board, or multi-board design, careful up front specification work will pay the most dividends. However, the overall process may be simpler than using multiple engineering groups to get a job done - communication issues are often minimalised.
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