Large version of image here

This approach allows customers to fully model the packet processing functions of an FPGA in their own system simulation environment and make decisions about HW/SW packet processing tradeoffs. Octera delivers the required packet processing modules as 'C++' classes. Once the modeling as been completed the 'C++' model of the FPGA is integrated back into Octera's own design environment. here we combine the model with our own packet generator and bus functional models to create the RTL for the proposed FPGA. Once developed and verified the operation of the FPGA is compared to the 'C++ model' to ensure it provides the correct functionality. Octera has also developed a HW platform that can be used to deliver the FPGA design in a suitable form for customer inter-operability test later in the development. the benefit of this approach are:

• Modeling of the FPGA HW is performed up front. This allows intelligent HW/SW trade-offs to be made at a system architecture level
• Once modeled, the C++ class is used by Octera as a 'gold standard' of the FPGA required functionality
• Many packet processing modules are available from octera off-the-shelf and we can quickly deliver custom modules as needed.

Our products

• Octera's packet processing FPGA co-simulation environment
• 10Gig custom XAUI bridge reference design

Using an Independent Design Group

• When to use an IDG
• What to expect
• Project phases
• Useful documents

Technology

• FPGA
• Structured ASIC
• ASIC
• Board and System

Tips and Techniques

• FPGA vs. ASIC
• Intellectual property