Semiconductor Technology

Without a doubt semiconductor technology has driven the biggest changes in modern electronic system design. The relentless march of new semiconductor process technology continues - and seems that it will continue for another decade or so. As a result, year on year, semiconductor components have got bigger, faster, more complex and the cost per gate has continued to fall. On the flip side, the cost of designing and tooling for a component has risen to the point where only high volume applications can typically justify a complete custom design. This has led to the rise of the FPGA and more recently the structured ASIC - devices with a much lower barrier to entry that can be used to customize your design.

Today's cutting edge process technology is 65nm, with some bleeding edge designs appearing in 45nm. The workhorse of most custom silicon are the 90nm and 130nm processes. 180nm processes have typically been completely amortized at this point and can therefore be very cost effective.

One of the huge advantages in using pre-designed silicon, such as FPGAs or structured ASICs, is that you get access to a leading edge process technology where the cost of development is amortized over millions of parts. In FPGA, this barrier is actually lowered to zero - the only engineering cost is your time, some inexpensive tools and the cost of the part. As of writing (Feb. 2007) it appears that Altera is emerging as the only company with a successful structured ASIC product family - due no doubt to the FPGA driven design path. Therefore structured ASIC design flow now closely resembles the FPGA design flow - in fact in some cases is exactly the same. It remains to be seen what Altera's next generation of structured ASICs (Hardcopy3) will actually look like.

Comparing FPGA, structured ASIC and FPGA we get the following features and benefits of each technology:

FPGA	Structured ASIC (Altera)	ASIC
Lowest NRE - zero	Medium NRE - 10-20% of full ASIC	Highest NRE
Shortest physical design time - a few hours	Medium physical design time - 6-8 weeks	Longest physical design time - 6 months plus
Highest unit cost	Medium unit cost	Lowest cost
Highest power consumption	Medium power consumption	Lowest power consumption
Instant design changes	Design changes affect metal layers only	Design changes can be a complete re-spin
FPGA style design code	FPGA style design code	ASIC style design code
Embedded IP - SERDES, processor	Some embedded IP (similar to FPGA, no Serdes)	No embedded IP. Start with a blank sheet
Low density (0-2M gates)	Similar to prototype FPGA	High density (20M gates +)

Selecting the right technology for your design is one of the major decisions that will be made and will affect every aspect of the process. It is also possible to begin in one technology and move to another - but be warned - design techniques between an FPGA and an ASIC vary dramatically. Broadly it is possible to design for one, or the other, but not for both (or not so good performance is achieved on both). Deciding, in advance, which is the final technology you are going to use, should begin right at the start of the project and will lead the rest of the design process.

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