Structured ASICs
Structured ASICs have not lived up to their initial promise, with perhaps, one exception - Altera's Hardcopy family. All other vendors tackled half of the problem - the high cost of physical design / mask sets from netlist to a chip. Without a doubt they all offered advantages in this process at the cost of some flexibility. However, the cost and complexity of the front-end portion of the design remained untouched by LSI, NEC and the others. Customers still had to develop complex RTL, verify it, and most importantly freeze the code before beginning the structured design. This meant that very few companies took the plunge. Add in the difficulties in such areas as new tool flows and most structured ASICs appeared and disappeared from the market all in the course of a few years. One company, Altera, took a different approach. They insisted the design had to be completed in an FPGA first. They then offered to convert the FPGA design files into a structured chip which would perform faster and have lower power than the FPGA. This approach has been and continues to be successful in the market place.

We highly recommend considering structured ASICs in certain applications, such as when ASIC speed, power consumption and density is a must but volume or schedule do not allow for a full custom chip.

Structured ASIC Embedded IP and Fabric
One of the huge advantages that structured ASICs have over ASICs is that the silicon vendor has with forethought embedded some IP onto the chip so the customer doesn't have to go through the complex process themselves. The IP found on a structured ASIC 'slice' or 'base array' consists of: memory, the I/O ring, the power grid and all of the non-metal silicon layers.

These elements have been pre-designed and laid out, signal integrity testing has been completed and they are guaranteed to work as planned in the final design. In addition, each vendor provides a 'sea of gates' which the customer uses to implement their proprietary logic by interconnecting the gates using the chip's metal layers. Some vendors provide their own tools while others use industry standard ASIC tools with specialized libraries. Vendors also provide some 'soft' IP cores that have been pre-laid out for the structured ASIC technology.

Typical cores in this category are:

• DDR, DDR2 and DDR3 memory controllers
• PCIe
• Storage protocols; SATA, SAS and Fibre Channel

All in all structured ASICs are an interesting addition to the custom digital design world and we expect to see their use grow dramatically over the next few years.